Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation

被引：0

作者：

Ercan, Furkan ^{[1
]}

Muhtaroglu, Ali ^{[2
]}

机构：

[1] Middle East Tech Univ, Sustainable Environm & Energy Syst, Northern Cyprus Campus, TR-10 Guzelyurt, Mersin, Turkey

[2] Middle East Tech Univ, Dept Elect & Elect Engn, TR-10 Guzelyurt, Mersin, Turkey

来源：

2015 5TH INTERNATIONAL CONFERENCE ON ENERGY AWARE COMPUTING SYSTEMS & APPLICATIONS (ICEAC) | 2015年

关键词：

arithmetic multiplier; power; delay performance; counter; parallel multiplication; PDP;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity.

引用

页数：4

共 44 条

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