VLSI Design, Implementation and Analysis of Low Power Montgomery Multiplier

This paper presents an efficient algorithm and Processing Element (PE) architecture for a Multiple Word Radix 4 Montgomery Modular (MWR4MM) multiplier. This architecture is developed considering many design factors such as performance and scalability in addition to an important design factor that is power consumption. The performance and scalability design factors are considered previously in many publications but power consumption still the greatest challenge that we face in this research area. To increase performance, we used a recoding scheme that eliminates the reduction step in the Montgomery algorithm and the PE architecture is based on the Carry-Save Adder (CSA). To achieve scalability, we implement the algorithm based on the multiple-word operation. Lastly to lower power consumption, we devised several effective techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals. Our Hardware implementation results show that the presented radix 4 architecture has a significant gain in reducing the total computation time and power consumption over other recent architectures.