Power Analysis of a Montgomery Modular Multiplier for Cryptosystems

被引:0
|
作者
Kakde, Sandeep [1 ]
Badwaik, Shailendra [2 ]
Deodhe, Yeshwant [1 ]
机构
[1] YC Coll Engn, Deptt Elect Engn, Nagpur, Maharashtra, India
[2] Singhad Coll Engn, Dept Elect Engn, Pune, Maharashtra, India
关键词
Modular operation; Modular exponentiation; Montgomery multiplication; FPGA; EXPONENTIATION;
D O I
10.1109/ICMIRA.2013.14
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Modular multiplication is the main task to be performed while doing the encryption and decryption algorithms. The main contribution of this paper is to implement modular multiplier using Montgomery algorithm for RSA encryption and decryption. Network security plays an important role in day-to-day communication systems. Many algorithms are developed in order to secure the data. These uses Ripple Carry Adders, Carry Look ahead Adder and Carry Save Adders (CSA's) to perform the large word length Addition's required by this algorithm when used for RSA encryption and decryption. For operand lengths of 128-bits and greater, the percentage gain in data throughput rate outweighs the percentage increase in silicon area. The dynamic power will also increase as the switching activity increases. Moreover, for a 256-bit operand length, typical of what is required in many future generation applications is the dynamic power reduction.
引用
收藏
页码:37 / 41
页数:5
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