Montgomery modular multiplication architecture for public key cryptosystems

被引：0
|
作者：
McLoone, M [1 ]
McIvor, C [1 ]
McCanny, J [1 ]
机构：
[1] Queens Univ Belfast, Inst Elect Commun & Informat Technol, Belfast, Antrim, North Ireland
来源：
2004 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a novel hardware architecture of the Coarsely Integrated Hybrid Scanning (CIHS) algorithm which performs Montgomery modular multiplication. The CIHS algorithm integrates the multiplication and reduction steps involved in modular multiplication. When implemented on a Virtex XC2VP50 device, the architecture can perform 128-bit modular multiplication at a data-rate of 160 Mbps and 256-bit modular multiplication at 216 Mbps. To the authors' knowledge, these are the first reported performance figures for a hardware CIHS algorithm architecture to be reported in the literature. A methodology for generating Montgomery multiplication test vectors is also described.
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页码：349 / 354
页数：6
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