An efficient CSA architecture for montgomery modular multiplication

被引：22
|
作者：
Zhang, Yuan-Yang [1 ]
Li, Zheng [1 ]
Yang, Lei [1 ]
Zhang, Shao-Wu [1 ]
机构：
[1] Informat Engn Univ, Inst Electron Technol, Zhengzhou 450004, Peoples R China
来源：
MICROPROCESSORS AND MICROSYSTEMS | 2007年 / 31卷 / 07期
关键词：
Montgomery algorithm; addition; CSA; FPGA;
D O I：
10.1016/j.micpro.2006.12.003
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Montgomery multipliers of carry save adder (CSA) architecture require a full addition to convert the carry save representation of the result into a conventional form. In this paper, we reuse the CSA architecture to perform the result format conversion, which leads to small area and fast speed. The results of implementation on FPGAs show that the new Montgomery multiplier is about 113.4 Mbit/s for 1024-bit operands at a clock of 114.2 MHz. (c) 2007 Elsevier B.V. All rights reserved.
引用
收藏
页码：456 / 459
页数：4
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