New systolic modular multiplication architecture for efficient Montgomery multiplication

被引:1
|
作者
Choi, Se-Hyu [1 ]
Lee, Keon-Jik [1 ]
机构
[1] Kyungpook Natl Univ, Sch Architectural Civil Environm & Energy Engn, Taegu 702701, South Korea
来源
IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 02期
关键词
Montgomery; modular multiplication; systolic array;
D O I
10.1587/elex.11.20141051
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose a new low complexity Montgomery algorithm enabling the efficient selection of the quotient value necessary for an exact division in Montgomery multiplication. We also present two new systolic multipliers which use similar data flows as described in the most significant bit (MSB)-first GF(2(m)) multiplier in [1]. The proposed parallel and serial multipliers have less hardware and time complexities compared to related multiplier. The serial multiplier can be well applied to space-limited hardware. Furthermore, our proposed systolic multipliers include regularity, modularity, local interconnection, and unidirectional data flow features.
引用
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页数:7
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