Energy delay analysis of partial product reduction methods for parallel multiplier implementation

被引：0
|
作者：
Pillai, RVK [1 ]
AlKhalili, D [1 ]
AlKhalili, AJ [1 ]
机构：
[1] CONCORDIA UNIV,MONTREAL,PQ,CANADA
来源：
1996 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - DIGEST OF TECHNICAL PAPERS | 1996年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
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页码：201 / 204
页数：4
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