共 50 条
- [12] Thermal performance of 3D IC integration with Through-Silicon Via (TSV) Chien, H.-C. (Jack_Chien@itri.org.tw), 1600, IMAPS-International Microelectronics and Packaging Society (09):
- [13] Thermal-Mechanical Reliability Assessment of TSV Structure for 3D IC Integration PROCEEDINGS OF THE 2016 IEEE 18TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2016, : 758 - 764
- [14] Research on TSV Positioning in 3D IC Placement 2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2011,
- [15] A TSV Alignment Design for Multilayer 3D IC PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
- [16] Distributed Multi TSV 3D Clock Distribution Network in TSV-based 3D IC 2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 87 - 90
- [17] TSV Interposer Fabrication for 3D IC Packaging 2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 431 - 437
- [18] TSV modelling in 3D IC thermoelectric simulation 2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, : 678 - 681
- [19] Electrical Testing of Blind Through-Silicon Via (TSV) for 3D IC Integration 2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 564 - 570
- [20] Integration of CNT in TSV (≤5 μm) for 3D IC Application and Its Process Challenges 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,