A Method of Gate-Level Circuit Yield Calculation Based on PTM

Many yield models have mainly focused on the system-level circuit, which ignores the effect of circuit structure on yield. Combining the layout structure information of the gate-level circuit, this paper firstly analyzed the growth characteristics of defects over aging time, topological structure, defect density of generalized gates and yield loss mechanisms. Second, the calculation method of the defect removal rate in aging was given, and then probability models of the yield loss of generalized gates were proposed. With consideration of the topological structure information of circuits, combining the above-mentioned models, the yields of some benchmark circuits were calculated by the iterative PTM method. Finally, the proposed model is validated by comparing its predictions with the results obtained by Poisson distribution, negative binomial distribution, and exponential distribution models. In addition, the effects of process parameters, aging time, and fault-tolerance techniques on circuit yield are analyzed, and some significant conclusions are made.