A dynamic timing delay for accurate gate-level circuit simulation

被引：0

作者：

Tang, T

Zhou, X

机构：

来源：

PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 1996年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models.

引用

页码：325 / 327

页数：3

共 50 条

[1] Temporal Parallel Gate-level Timing Simulation
Kim, Dusung
Ciesielski, Maciej
Shim, Kyuho
Yang, Seiyang
[J]. HLDVT: 2008 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2008, : 111 - +
[2] Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis
Chen, Kai
Kim, Young Hwan
[J]. 2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT), 2015,
[3] GATE-LEVEL SIMULATION
DABREU, MA
[J]. IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (06): : 63 - 71
[4] Timing Errors in STA-based Gate-Level Simulation
Simoglou, Stavros
Sotiriou, Christos
Blias, Nikolaos
[J]. 2020 26TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS ASYNC 2020, 2020, : 1 - 2
[5] Gate-Level Modeling for CMOS Circuit Simulation with Ultimate FinFETs
Chevillon, Nicolas
Madec, Morgan
Lallement, Christophe
[J]. PROCEEDINGS OF THE 2012 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2012, : 22 - 29
[6] Fast STA Prediction-based Gate-level Timing Simulation
Ahmad, Tariq B.
Ciesielski, Maciej J.
[J]. 2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
[7] A compact gate-level energy and delay model of dynamic CMOS gates
Rosselló, JL
de Benito, C
Segura, J
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2005, 52 (10) : 685 - 689
[8] DISTRIBUTING GATE-LEVEL DIGITAL TIMING SIMULATION OVER ARRAYS OF TRANSPUTERS
WOOD, KR
[J]. CONCURRENCY-PRACTICE AND EXPERIENCE, 1991, 3 (04): : 367 - 379
[9] An Accurate Gate-level Stress Estimation for NBTI
Han, Sangwoo
Lee, Junho
Kim, Byung-Su
Kim, Juho
[J]. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13 (02) : 139 - 144
[10] Library compatible Ceff for gate-level timing
Sheehan, BN
[J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 826 - 830

← 1 2 3 4 5 →