Design of a low-power 8 x 8-bit parallel multiplier using MOS current mode logic circuit

被引：1

作者：

Kim, J. B. ^{[1
]}

Lee, Y. S. ^{[1
]}

机构：

[1] Kangwon Natl Univ, Dept Elect Engn, Chunchon, South Korea

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 2007年 / 94卷 / 10期

关键词：

MOS current logic (MCML); low-power circuit; multiplier; arithmetic unit;

D O I：

10.1080/00207210701679926

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes an 8 x 8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8 x 8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35 mu m standard CMOS process.

引用

页码：905 / 913

页数：9

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