Design of a low-power 8 x 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8 x 8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8 x 8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35 mu m standard CMOS process.