Design of Low Power 8-Bit DAC Using PTM-LP Technology

被引：2

作者：

Huq, S. M. Ishraqul ^{[1
]}

Islam, Sumaiya ^{[1
]}

Saqib, Nazmus ^{[1
]}

Biswas, Satyendra N. ^{[1
]}

机构：

[1] Ahsanullah Univ Sci & Technol, Dept Elect & Elect Engn, Dhaka 1208, Bangladesh

来源：

2017 INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRICAL, ELECTRONICS AND COMPUTING TECHNOLOGIES (ICRTEECT) | 2017年

关键词：

DAC; Current steering; low power; DNL; INL;

D O I：

10.1109/ICRTEECT.2017.30

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With emerging high performance digital circuits, the need for data converters with high accuracy, high speed and low power for various kinds of applications has increased greatly. Extensive researches are being conducted in order to decrease the size of data converters to obtain low power and high speed characteristics. Digital to Analog Converters (DACs) convert digital signals to analog signals. This paper presents the design of a low power, 8-bit, segmented current steering DAC using PTM 32nm technology. The simulation was carried out in LTSpice software. The DNL and INL of the converter was measured to be 0.37 LSB and 1.5 LSB respectively. With an input date rate of 1GHz, the SFDR was measured to be 33dB. The total power consumption of the converter was 0.257mW. The same design was simulated with PTM 16nm technology and results were compared with each other and other recent works.

引用

页码：64 / 69

页数：6

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