COMPRESSOR BASED 8x8 BIT VEDIC MULTIPLIER USING REVERSIBLE LOGIC

被引：0

作者：

Lakshmi, G. Sree ^{[1
]}

Fatima, Kaleem ^{[2
]}

Madhavi, B. K. ^{[3
]}

机构：

[1] GCET, Hyderabad, Andhra Pradesh, India

[2] MJCET, Hyderabad, Andhra Pradesh, India

[3] Sridevi Womens Coll, Hyd, India

来源：

PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS) 2016 | 2016年

关键词：

Reversible gates; Compressors; Vedic Multiplier; Low power; LOW-POWER; 3-2; HIGH-SPEED;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Reversible logic gates became very important and computing paradigm having its applications in low power CMOS technologies and Quantum computing [5]. Reversible logics are used to reduce the depth of the circuits [6]. This paper introduces a new architecture of 4: 2 Compressorbased Vedic 8x8 bit Multiplier using reversible logic and is compared with conventional multipliers using Reversible logic and it was observed that the parameters like Hardware Complexity, power and Delay are improved over other Reversible multipliers. The design is simulated, synthesized and power estimation was done using TSMC 180nm technology using Cadence Digital tools.

引用

页码：174 / 178

页数：5

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