A 32 BIT MAC Unit Design Using Vedic Multiplier and Reversible Logic Gate

被引：0

作者：

Anitha, R. ^{[1
]}

Deshmukh, Neha ^{[1
]}

Agarwal, Prashant ^{[1
]}

Sahoo, Sarat Kumar ^{[1
]}

Karthikeyan, S. Prabhakar ^{[1
]}

Reglend, Jacob ^{[2
]}

机构：

[1] VIT Univ, Sch Elect Engn, Vellore, Tamil Nadu, India

[2] Noorul Islam Univ, Dept Elect & Elect Engn, Kanyakumari, India

来源：

2015 INTERNATIONAL CONFERENCED ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT-2015) | 2015年

关键词：

Reversible Logic; Urdhava Triyagbhayam; Quantum Computing; Kogge Stone Adder; HIGH-SPEED;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area.The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 14 2 and synthesis is done in both RTL compiler using cadence as well as Xilinx The chip design for the proposed MAC is also carried out.

引用

页数：6

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