Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology

An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node. GAA device structure is optimized to achieve maximum electrostatics driven performance. Vertically stacked lateral nanosheet devices display superior performance and area scaling as compared to the conventional finFET and GAA technologies. Gate-all-around nanosheet (NS) devices with sheet width of 8nm enhance the performance of a CMOS inverter by 18.67% while reducing the area by 14.54% as compared to the finFETs with horizontal device footprints of 25nm.