Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology

被引：1
|
作者：
Gundu, Anil Kumar [1 ]
Kursun, Volkan [2 ]
机构：
[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Kowloon, Clear Water Bay, Hong Kong, Peoples R China
[2] Norwegian Univ Sci & Technol, Dept Elect Syst, N-7034 Trondheim, Norway
来源：
34TH IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (SOCC) | 2021年
关键词：
Gate-all-around; stacked nanosheet; footprint; short-channel effect; minimum sized inverter;
D O I：
10.1109/SOCC52499.2021.9739517
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node. GAA device structure is optimized to achieve maximum electrostatics driven performance. Vertically stacked lateral nanosheet devices display superior performance and area scaling as compared to the conventional finFET and GAA technologies. Gate-all-around nanosheet (NS) devices with sheet width of 8nm enhance the performance of a CMOS inverter by 18.67% while reducing the area by 14.54% as compared to the finFETs with horizontal device footprints of 25nm.
引用
收藏
页码：25 / 28
页数：4
相关论文
共 50 条
  • [21] Geometrical Variability Impact on the Performance of Sub-3 nm Gate-All-Around Stacked Nanosheet FET
    Yadav, Nisha
    Jadav, Sunil
    Saini, Gaurav
    [J]. SILICON, 2022, 14 (16) : 10681 - 10693
  • [22] Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node
    Rzepa, Gerhard
    Bhuwalka, Krishna K.
    Baumgartner, Oskar
    Leonelli, Daniele
    Karner, Hui-Wen
    Schanovsky, Franz
    Kernstock, Christian
    Stanojevic, Zlatan
    Wu, Hao
    Benistant, Francis
    Liu, Changze
    Karner, Markus
    [J]. 2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM, 2022,
  • [23] 3D Monte Carlo Simulation of Gate-All-Around Germanium nMOSFET
    Zhu, Shufang
    Wei, Kangliang
    Du, Gang
    Liu, Xiaoyan
    [J]. 2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2011,
  • [24] Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
    Vashishtha, Vinay
    Clark, Lawrence T.
    [J]. MICROELECTRONICS JOURNAL, 2021, 107
  • [25] Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs
    Mohapatra, E.
    Dash, T. P.
    Jena, J.
    Das, S.
    Maiti, C. K.
    [J]. PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2020), 2020, : 331 - 334
  • [26] Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications
    Thakur, Rajiv Ranjan
    Chaturvedi, Nidhi
    [J]. NANO, 2021, 16 (08)
  • [27] System Design Technology Co-Optimization for 3D Integration at <5nm nodes
    Song, S. C.
    Nallapati, Giri
    Khan, Irfan
    Nikfar, Nader
    Yan, Bohan
    Miranda, Miguel
    Lim, Bruce
    Nagarajan, Mali
    Park, Joon-Young
    Srinivas, Vaishnav
    Langari, Reza
    Chava, Bharani
    Sanaka, Venu
    Boynapalli, Venu
    Gupta, Paras
    Pandey, Shree
    Xie, Biancun
    Feng, Peijie
    Choi, Jihong
    Rakshit, Titash
    Shenoy, Ravi
    Nemani, Mahadev
    Verrilli, Colin
    Zhu, John
    Chen, Jun
    Nakamoto, Mark
    Zhao, Lily
    Sun, Yangyang
    Atallah, Francois
    Kim, Jonghae
    Attar, Rashid
    Chidambaram, Chidi
    [J]. 2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
  • [28] Stacked SiGe/Si I/O FinFET device preparation in a vertically stacked gate-all-around technology
    Zhao, Fei
    Li, Yan
    Luo, Huaizhi
    Jia, Xiaofeng
    Zhang, Jiayi
    Mao, Xiaotong
    Li, Yongliang
    [J]. MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2023, 164
  • [29] ESD Diodes in a Bulk Si Gate-All-Around Vertically Stacked Horizontal Nanowire Technology
    Chen, S. -H.
    Hellings, G.
    Scholz, M.
    Linten, D.
    Mertens, H.
    Ritzenthaler, R.
    Boschke, R.
    Groeseneken, G.
    Horiguchi, N.
    [J]. 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,
  • [30] Thermal Coupling Among Channels and Its DC Modeling in Sub-7-nm Vertically Stacked Nanosheet Gate-All-Around Transistor
    Liu, Renhua
    Li, Xiaojin
    Sun, Yabin
    Li, Fei
    Shi, Yanling
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (12) : 6563 - 6570
12345