Stacked SiGe/Si I/O FinFET device preparation in a vertically stacked gate-all-around technology

被引：1

作者：

Zhao, Fei ^{[1
,2
]}

Li, Yan ^{[3
]}

Luo, Huaizhi ^{[3
]}

Jia, Xiaofeng ^{[1
,2
]}

Zhang, Jiayi ^{[1
,2
]}

Mao, Xiaotong ^{[1
,2
]}

Li, Yongliang ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Integrated Circuit Adv Proc Ctr, Beijing 100029, Peoples R China

[2] Univ Chinese Acad Sci, Sch Integrated Circuits, Beijing 100049, Peoples R China

[3] Beijing Informat Sci & Technol Univ, Sch Appl Sci, Beijing 100192, Peoples R China

来源：

MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING | 2023年 / 164卷

关键词：

Stacked SiGe; Si I; O FinFET; STI densification annealing; RTA; ALDSiO2;

D O I：

10.1016/j.mssp.2023.107634

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, a stacked SiGe/Si input-output (I/O) FinFET device preparation with an optimized thermal budget and atomic layer deposition (ALD) SiO2 gate dielectric is investigated. First, a vertical and smooth profile of the stacked SiGe/Si fin without obvious Ge diffusion and SiGe oxidation is maintained by developing an optimized STI densification process using rapid thermal annealing (RTA) of 850 degrees C for 30s. Then, a high-quality ALD SiO2 with thickness of 3 nm suitable for the gate dielectric layer of I/O device is verified based on MOS capacitance (CAP) structure. Finally, a stacked SiGe/Si I/O FinFET targeting 1.8V operating voltage (VDD) is successfully prepared with good physical structure and electrical characteristics. Meanwhile, its maximum operating voltage (Vmax) for a 10 years lifetime at a failure rate of 0.01% can reach to 2.03V. Therefore, these newly developed processes are practical for the stacked SiGe/Si I/O FinFET device in a vertically stacked GAA technology.

引用

页数：6

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