The Optimization of Gate All Around-L-ShapedBottom Select Transistor in 3D NAND Flash Memory

被引：2
|
作者：
Zou, Xingqi [1 ,3 ]
Jin, Lei [1 ,3 ,4 ]
Jiang, Dandan [2 ]
Zhang, Yu [1 ,3 ]
Chen, Guoxing [4 ]
Xia, Zhiliang [1 ,3 ,4 ]
Huo, Zongliang [1 ,3 ,4 ]
机构：
[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
[2] Chengdu Univ Informat Technol, Coll Commun Engn, Chengdu 610103, Sichuan, Peoples R China
[3] Univ Chinese Acad Sci, Beijing 100049, Peoples R China
[4] Yangtze Memory Technol Co Ltd YMTC, Wuhan 430205, Hubei, Peoples R China
来源：
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | 2018年 / 18卷 / 08期
基金：
中国国家自然科学基金;
关键词：
L-Shaped Bottom Select Transistor; Threshold Voltage (Vth); Distribution; Boosting; Rounding; Three Dimensional (3D) NAND;
D O I：
10.1166/jnn.2018.15401
中图分类号：
O6 [化学];
学科分类号：
0703 ;
摘要：
In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor). With implant dose increasing in vertical channel, BSG Vth has much more tighter V, distribution, which is beneficial for boosting potential improvement and program disturbance suppression. Meanwhile, BSG corner rounding is proposed to improve the characteristic of BSG. Experiment and TCAD simulation data are matches quite well, giving a way to improve cell characteristics distribution and self-boosting potential control in high density 3D NAND array.
引用
收藏
页码：5528 / 5533
页数：6
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