Optimization of Performance and Reliability in 3D NAND Flash Memory

被引：16
|
作者：
Ouyang, Yingjie [1 ,2 ,3 ]
Xia, Zhiliang [1 ,2 ,3 ]
Yang, Tao [1 ,2 ,3 ]
Shi, Dandan [1 ,2 ,3 ]
Zhou, Wenxi [3 ]
Huo, Zongliang [1 ,2 ,3 ]
机构：
[1] Univ Chinese Acad Sci, Beijing 100049, Peoples R China
[2] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
[3] Yangtze Memory Technol Co Ltd, Wuhan 430205, Peoples R China
来源：
IEEE ELECTRON DEVICE LETTERS | 2020年 / 41卷 / 06期
关键词：
Tunneling; Three-dimensional displays; Flash memories; Dielectric constant; Logic gates; Electron traps; Reliability; Tunnel layer; program; erase speed; threshold voltage shift; 3D NAND flash memory; BANDGAP-ENGINEERED SONOS; BE-SONOS; RETENTION; SIO2;
D O I：
10.1109/LED.2020.2987087
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure. The optimal thickness of O1 layer is found. Under the optimal condition, program speed increased by 19% compared with no O1 layer deposition, though erase speed is slightly decreased by about 7%, the initial threshold voltage shift is improved greatly. Experimental results demonstrate that there are complex mechanisms affected by the dielectric constant, band barrier and equivalent oxide thickness. The optimization of O1 layer is useful towards an understanding of program/erase speed and retention characteristics.
引用
收藏
页码：840 / 843
页数：4
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