Low Power Conditional Pulse Control with Transmission Gate Flip-Flop

被引：0

作者：

Berwal, Deepak ^{[1
]}

Kumar, Ashish ^{[1
]}

Kumar, Yogendera ^{[1
]}

机构：

[1] Galgotias Univ, VLSI Div, Sch Elect Elect & Commun Engn, Plot 2,Sect 17-A, Greater Noida 201301, UP, India

来源：

2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION & AUTOMATION (ICCCA) | 2015年

关键词：

Flip-Flops; transmission gate; conditional pulse; low power; HIGH-PERFORMANCE; DESIGN;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In the present work, Low Power Conditional Pulse Control with Transmission Gate Flip-Flop (CPCTG-FF) design based on signal feed through scheme is proposed. The proposed design removes the long discharging path problem with intermediate nodes using the pulse generation control logic with transmission gate (which facilitates a faster discharge operation). Transmission gate and a NMOS are used to control the input data and clock circuit to reduce the power dissipation along the critical path. As a result, very low power dissipation occurs when there is no switching. T-Spice (Tanner 14.1) is used for the simulation purposes. All simulation results are based on using CMOS 90-nm technology at 500MHz clock frequency. Its maximum power saving compared to conditional pulse enhancement scheme flip-flop [1] is up to 16.84% and compared to signal feed through scheme designs [2] is up to 37.19%.

引用

页码：1358 / 1362

页数：5

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