Low power, high reliability magnetic flip-flop

被引:21
|
作者
Lakys, Y. [1 ]
Zhao, W. S. [1 ]
Klein, J. -O. [1 ]
Chappert, C. [1 ]
机构
[1] Univ Paris Sud, UMR8622, IEF, F-91405 Orsay, France
关键词
D O I
10.1049/el.2010.2039
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new design of a non-volatile magnetic flip-flop is presented. The use of a magnetic tunnel junction (MTJ) to store the information brings non-volatility to logic circuits and promises zero standby power. It is based on the thermally assisted switching (TAS) approach and the pre-charge sense amplifier. By using STMicroelectronics' CMOS 0.13um design kit and a precise TAS-MTJ compact model, transient functional simulations and Monte Carlo statistical analysis have been carried out to show, respectively, its low power and high reliability performances.
引用
收藏
页码:1493 / U31
页数:2
相关论文
共 50 条
  • [1] A new low power high performance flip-flop
    Sayed, Ahmed
    Al-Asaad, Hussain
    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 723 - +
  • [2] Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost
    Cai, Hao
    Wang, You
    Naviner, Lirida Alves de Barros
    Zhao, Weisheng
    IEEE TRANSACTIONS ON MAGNETICS, 2016, 52 (08)
  • [3] A high-speed low-power D flip-flop
    Chandrasekaran, R
    Lian, Y
    Rana, RS
    2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 152 - 155
  • [4] Design & Implementation of High Speed Low Power Scan Flip-Flop
    Janwadkar, Sudhanshu
    Kolte, Mahesh T.
    2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 2010 - 2014
  • [5] A Low-Power CMOS Flip-Flop for High Performance Processors
    Meher, Preetisudha
    Mahapatra, Kamala Kanta
    TENCON 2014 - 2014 IEEE REGION 10 CONFERENCE, 2014,
  • [6] Design and Analysis of High-Performance and Low-Power Quaternary Latch, Quaternary D Flip-Flop and XY Flip-Flop
    Shadwani, Mayank
    Bansal, Urvashi
    INDIAN JOURNAL OF PURE & APPLIED PHYSICS, 2022, 60 (12) : 1004 - 1015
  • [7] Modified Scan Flip-Flop for Low Power Testing
    Mishra, Amit
    Sinha, Nidhi
    Satdev
    Singh, Virendra
    Chakravarty, Sreejit
    Singh, Adit D.
    2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, : 367 - 370
  • [8] Low Power Dual Edge Triggered Flip-Flop
    Saini, Nitin Kumar
    Kashyap, Kamal K.
    2014 INTERNATIONAL CONFERENCE ON SIGNAL PROPAGATION AND COMPUTER TECHNOLOGY (ICSPCT 2014), 2014, : 125 - 128
  • [9] The Cross Charge-control Flip-Flop: a low-power and high-speed flip-flop suitable for mobile application SoCs
    Hirata, A
    Nakanishi, K
    Nozoe, M
    Miyoshi, A
    2005 Symposium on VLSI Circuits, Digest of Technical Papers, 2005, : 306 - 307
  • [10] High-performance and low-power conditional discharge flip-flop
    Zhao, PY
    Dakwish, TK
    Bayoumi, MA
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (05) : 477 - 484