Design & Implementation of High Speed Low Power Scan Flip-Flop

Over the years, The semiconductor industry has made tremendously impressive improvement in terms of density of very large-scale integrated (VLSI) circuits. Increasing demand for System on Chip(SoC) design can be viewed as a consequence of this trend. In SoC testing, Scan-path test is being used widely to reduce test generation complexity for circuit containing storage devices and feedback paths with combinational logic. Since a lot of scan flip flops are used in scan path testing of SoC, improving the performance of scan flip-flops is significantly important. In the past decade, many flip-flop designs have been proposed which incorporate Scan functionality into flip-flop architecture, to combat flip-flop latency. However, no attempts have been made towards FPGA implementation of these designs. In this paper, we have attempted to provide a FPGA approach to solve the issue. We have implemented the Dynamic node scan Flip-flop on Spartan 6 family device. Our scan flip-flop architecture has 14.38% reduction in Power-Delay Product over the previous architecture.