A low voltage CMOS square law analog multiplier

被引：3
|
作者：
Tarim, TB [1 ]
Ismail, M [1 ]
机构：
[1] Texas Instruments Inc, Dallas, TX 75265 USA
来源：
1999 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, SSMSD 99 | 1999年
关键词：
D O I：
10.1109/SSMSD.1999.768581
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A multiplier composed of a low voltage square-law CMOS cell is introduced in this paper. The analysis of the square-law cell is given. The multiplier operates in the saturation region with a fully balanced input signal. Initial simulations were done for 0.8 mu m n-well process using BSIM3 model parameters. The circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 99.4MHz and P-dis=1.5mW for a bias current of 120 mu A. The THD is less then -51dB and -49dB for fixed input voltages V3 and V1, respectively,for a 1MHz, 0.5V peak-to-peak sinusoidal input.
引用
收藏
页码：5 / 8
页数：4
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