Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell

被引：0
|
作者：
Changku Hwang
Akira Hyogo
Hong-sun Kim
Mohammed Ismail
Keitaro Sekine
机构：
[1] Hitachi America,Research & Development Division
[2] Ltd.,Department of Electrical Engineering, Faculty of Science and Technology
[3] Science University of Tokyo,Solid
[4] The Ohio State University,State Microelectronics Laboratory, Department of Electrical Engineering
来源：
Analog Integrated Circuits and Signal Processing | 2000年 / 25卷
关键词：
analog signal processing; CMOS; low voltage; composite transistor; multiplier;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 μm N-well process with a 3 V supply are given.
引用
收藏
页码：347 / 350
页数：3
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