Low voltage high-speed CMOS square-law composite transistor cell

被引：0

作者：

Hwang, C ^{[1
]}

Hyogo, A

Kim, HS

Ismail, M

Sekine, K

机构：

[1] Hitachi Amer Ltd, Div Res & Dev, San Jose, CA 95134 USA

[2] Sci Univ Tokyo, Fac Sci & Technol, Dept Elect Engn, Noda, Chiba 2788510, Japan

[3] Ohio State Univ, Dept Elect Engn, Solid State Microelect Lab, Columbus, OH 43210 USA

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2000年 / 25卷 / 03期

关键词：

analog signal processing; CMOS; low voltage; composite transistor; multiplier;

D O I：

10.1023/A:1008394318240

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.

引用

页码：347 / 349

页数：3

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