Low-voltage CMOS four-quadrant multiplier

被引：11

作者：

Liu, SI

Chang, CC

机构：

[1] Department of Electrical Engineering, National Taiwan University, Taipei

来源：

ELECTRONICS LETTERS | 1997年 / 33卷 / 03期

关键词：

analogue multipliers; CMOS integrated circuits; multiplying circuits;

D O I：

10.1049/el:19970168

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new CMOS four-quadrant multiplier that can operate from supply voltages of +/-1.5V is presented. This circuit was fabricated in a standard 0.8 mu m single-poly double-metal CMOS process. Experimental results show that the nonlinearity can be kept <2% across the entire differential input voltage range of +/-0.8V. The total harmonic distortion is <2% with the differential input range up to +/-0.8V. The measured -3dB bandwidth of this multiplier is similar to 5MHz. It is expected to be useful in low-voltage analogue signal-processing applications.

引用

页码：207 / 208

页数：2

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