Compact low-voltage CMOS four-quadrant analogue multiplier

被引：12
|
作者：
Sawigun, C.
Demosthenous, A.
机构：
[1] Mahanakorn Univ Technol, Dept Elect Engn, Bangkok 10530, Thailand
[2] UCL, Dept Elect & Elect Engn, London WC1E 7JE, England
来源：
ELECTRONICS LETTERS | 2006年 / 42卷 / 20期
关键词：
D O I：
10.1049/el:20062093
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the subcurrents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 mu m CMOS process are provided.
引用
收藏
页码：1149 / 1151
页数：3
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