Compact low-voltage CMOS analog divider using a four-quadrant multiplier and biasing control circuit

被引：0
|
作者：
Padilla-Cantoya, Ivan [1 ]
机构：
[1] Inst Tecnol & Estudios Super Occidente ITESO, Dept Elect Sistemas & Informat DESI, Tlaquepaque, Jalisco, Mexico
来源：
2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2012年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A compact low-voltage analog divider is presented. The design is based on a four-quadrant multiplier and a differential transconductance amplifier as basic building blocks operating in voltage mode. A biasing control circuit to set the dc operational point that requires very few devices and offers continuous-time operation is included. Experimental results of a test chip in 0.5 mu m CMOS technology verify the proposed operation.
引用
收藏
页码：502 / 505
页数：4
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