Analog CMOS four-quadrant multiplier and divider

被引：0

作者：

Vlassis, S ^{[1
]}

Siskos, S ^{[1
]}

机构：

[1] Aristotelian Univ Salonika, Dept Phys, Elect Lab, GR-54006 Salonika, Greece

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: SYSTEMS, POWER ELECTRONICS, AND NEURAL NETWORKS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

An analog CMOS four-quadrant multiplier and a two-quadrant divider circuit are introduced. The multiplier operates for a power supply +/-1.5V and its differential input range is +/-1V with less than 0.2% linearity error. The THD is less than 0.3% with input range up to +/-0.8V. The divider offers the facility of independent control of the sensitivity and has acceptable precision useful in analog signal processing, fuzzy control and instrumentation applications. Experimental results verify the simulation ones demonstrating the feasibility of both circuits.

引用

页码：383 / 386

页数：4

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