Four-quadrant analog multiplier based on CMOS inverters

被引：0
|
作者：
Witold Machowski
Stanisław Kuta
Jacek Jasielski
机构：
[1] AGH University of Science and Technology,
来源：
Analog Integrated Circuits and Signal Processing | 2008年 / 55卷
关键词：
CMOS; Analog multiplier; LV circuits;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with digital CMOS, since there are only two transistors stacked-up between supply rails. Thus the supplying voltage of this circuit class is the lowest possible one for any particular CMOS technology. The operation principle based on symbolic analysis with simple square model has been fully confirmed by simulations with BSIM3v3 models provided by different silicon foundries and verified experimentally using one of them.
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页码：249 / 259
页数：10
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