A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair

被引：0

作者：

Chen, Weiping ^{[1
]}

Wang, Tianyang ^{[1
]}

Xu, Honglei ^{[1
]}

Liu, Xiaowei ^{[1
]}

机构：

[1] Harbin Inst Technol, MEMS Ctr, Harbin 150006, Heilongjiang, Peoples R China

来源：

MEMS/NEMS NANO TECHNOLOGY | 2011年 / 483卷

关键词：

Multiplier; CMOS Source Coupled Pair; Attenuator;

D O I：

10.4028/www.scientific.net/KEM.483.487

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5 mu m CMOS technology shows that under +/- 2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.

引用

页码：487 / 491

页数：5

共 50 条

[1] Four-quadrant analog multiplier based on CMOS inverters
Machowski, W.
Kuta, S.
Jasielski, J.
[J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, : 290 - +
[2] Four-quadrant analog multiplier based on CMOS inverters
Witold Machowski
Stanisław Kuta
Jacek Jasielski
[J]. Analog Integrated Circuits and Signal Processing, 2008, 55 : 249 - 259
[3] Four-quadrant analog multiplier based on CMOS inverters
Machowski, Witold
Kuta, Stanistaw
Jasielski, Jacek
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2008, 55 (03) : 249 - 259
[4] Analog CMOS four-quadrant multiplier and divider
Vlassis, S
Siskos, S
[J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: SYSTEMS, POWER ELECTRONICS, AND NEURAL NETWORKS, 1999, : 383 - 386
[5] CMOS Fully Differential CMOS Four-Quadrant Analog Multiplier
Mahmoud, Soliman A.
[J]. 2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2008, : 27 - 30
[6] A 1.2 V CMOS four-quadrant analog multiplier
Hsiao, SY
Wu, CY
[J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 241 - 244
[7] A DTMOS based Four-Quadrant Analog Multiplier
Ozer, Emre
[J]. ELECTRICA, 2020, 20 (02): : 207 - 217
[8] A four-quadrant analog multiplier using basic differential pair
Boonchu, B
Surakampontorn, W
[J]. TENCON 2004 - 2004 IEEE REGION 10 CONFERENCE, VOLS A-D, PROCEEDINGS: ANALOG AND DIGITAL TECHNIQUES IN ELECTRICAL ENGINEERING, 2004, : D290 - D293
[9] A 1.2-V CMOS four-quadrant analog multiplier
Blalock, BJ
Jackson, SA
[J]. 1999 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, SSMSD 99, 1999, : 1 - 4
[10] A New CMOS Four-quadrant Analog Multiplier with Differential Output
Saatlo, Ali Naderi
Amiri, Abolfazl
Asadpour, Loghman
[J]. 2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD), 2015,

← 1 2 3 4 5 →