Design and characterization of a 10 Gb/s clock and data recovery circuit implemented with phase-locked loop

被引：10

作者：

Song, JH ^{[1
]}

Yoo, TW ^{[1
]}

Ko, JH ^{[1
]}

Park, CS ^{[1
]}

Kim, JK ^{[1
]}

机构：

[1] ETRI, Opt Commun Dept, Taejon, South Korea

来源：

ETRI JOURNAL | 1999年 / 21卷 / 03期

关键词：

D O I：

10.4218/etrij.99.0199.0301

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A clock and data recovery circuit with a phase-locked Loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency- and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to 60 degrees C and showed no increase of error, This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

引用

页码：1 / 5

页数：5

共 50 条

[1] 10Gb/s clock extraction and data regeneration circuit implemented with phase-locked loop
Yoo, TW
Park, MS
[J]. 1997 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS I-III: HIGH FREQUENCIES IN HIGH PLACES, 1997, : 1713 - 1716
[2] Design of the clock recovery circuit with a phase-locked loop for 40 Gb/s optical receivers
Park, CH
Woo, DS
Kim, KW
Lim, SK
[J]. 34TH EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, 2004, : 757 - 759
[3] A 40 Gb/s clock and data recovery module with improved phase-locked loop circuits
Park, Hyun
Kim, Kang Wook
Lim, Sang-Kyu
Ko, Jesoo
[J]. ETRI JOURNAL, 2008, 30 (02) : 275 - 281
[4] 40 Gb/s clock recovery based on optical phase-locked loop
Department of Electronics Engineering, Tsinghua University, Beijing 100084, China
[J]. Guangxue Xuebao, 2007, 8 (1382-1386): : 1382 - 1386
[5] Implementation of a phase-locked loop clock recovery module for 40 Gb/s optical receivers
Park, CH
Woo, DS
Kim, TG
Lim, SK
Kim, KW
[J]. 2005 IEEE MTT-S International Microwave Symposium, Vols 1-4, 2005, : 2127 - 2130
[6] 80-to 10-Gb/s clock recovery using an electro-optic phase-locked loop
Carruthers, TF
Lou, JW
[J]. ECOC'01: 27TH EUROPEAN CONFERENCE ON OPTICAL COMMUNICATION, VOLS 1-6, 2001, : 284 - 285
[7] Design and verification of data acquisition clock circuit based on dual-loop phase-locked loop
Liu Z.
Gao G.
Yue J.
Cao J.
Du Y.
Ma H.
He J.
Ye Q.
Tang X.
Li Y.
Yang J.
Wei S.
[J]. He Jishu/Nuclear Techniques, 2022, 45 (10):
[8] A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
Rhee, W
Ainspan, H
Rylov, S
Rylyakov, A
Beakes, M
Friedman, D
Gowda, S
Soyuer, M
[J]. PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 81 - 84
[9] A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop
Shu, Guanghua
Saxena, Saurabh
Choi, Woo-Seok
Talegaonkar, Mrunmay
Inti, Rajesh
Elshazly, Amr
Young, Brian
Hanumolu, Pavan Kumar
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (04) : 1036 - 1047
[10] An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
Hsu, TY
Shieh, BJ
Lee, CY
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (08) : 1063 - 1073

← 1 2 3 4 5 →