A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop

A reference-less half-rate digital clock and data recovery ( CDR) circuit employing a phase-rotating phase-locked loop ( PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer ( JTRAN) bandwidth from jitter tolerance ( JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation ( BER < 10(-12)) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/ s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps(rms) / 44.0 ps(pp) when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves 134 dBc/ Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within +/- 0.2 LSB and +/- 0.4 LSB, respectively.