An all-digital phase-locked loop (ADPLL)-based clock recovery circuit

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell, These modules have been designed and verified on a 0.6-mu m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clack generator can generate any target clock rate f(clock); and 3) the function of nonreturn-to-zero clock recovery has a maximum f(clock)/4 recovering capability vith a locking range of (tau(input) + tau(input)/2), where tau(input) is the input period.