Direct Digital Synthesis-Based All-Digital Phase-Locked Loop

被引：0

作者：

Vezant, Benoit ^{[1
]}

Mansuy, Cedric ^{[1
]}

Bui, Hung Tien ^{[1
]}

Boyer, Francois-Raymond ^{[2
]}

机构：

[1] Univ Quebec Chicoutimi, Dept Appl Sci, Chicoutimi, PQ, Canada

[2] Ecole Polytech Montreal, Dept Comp Engn, Montreal, PQ, Canada

来源：

2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE | 2009年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper, we present an architecture for a PLL that is based on DDS and that can be implemented using all-digital components. The local oscillator is based on a DDS that is clocked by a local oscillator and that is synchronized to a crystal reference using a negative feedback which is similar to a PLL. Even though the DDS uses a ring oscillator, the proposed design can provide a precise output clock in presence of process and temperature variations. The resulting system has deterministic jitter that is equal to 1 period of the ring oscillator. The system was validated using MATLAB/Simulink and was implemented on a Cyclone II FPGA. Measured experimental results confirm that the system works as expected.

引用

页码：49 / +

页数：2

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