A New All-Digital Phase-Locked Loop Based on Single CPLD

被引：0

作者：

Shen, Weicong ^{[1
]}

Zhang, Fan ^{[1
]}

机构：

[1] Wuhan Univ Technol, Coll Informat Engn, Wuhan, Peoples R China

来源：

PROCEEDINGS OF 2016 8TH IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION SOFTWARE AND NETWORKS (ICCSN 2016) | 2016年

关键词：

digital phase-locked loop; frequency multiplication; single CPLD;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the development of digital circuit technology, digital phase-locked loop (DPLL) has been widely applied. But regard to the existing DPLL systems, both the range of the locked phase and the running speed can't meet the needs of the application in reality. The heart of the matter is the constraint of algorithm and structure. In order to improve the performance, we present a new all-digital phase-locked loop (ADPLL) in this paper. We adopted frequency tracking algorithm and phase tracking algorithm to composite frequency multiplying signal and phase-locked signal in a way similar to the DDS. All algorithms were loaded into a single CPLD. The CPLD which was customized to a DPLL has a good performance in the tests. Compared to the current ones, this one locks phase faster and the frequency range of the input signal is wider.

引用

页码：307 / 310

页数：4

共 50 条

[1] WIDEBAND ALL-DIGITAL PHASE-LOCKED LOOP
YAMAMOTO, H
MORI, S
[J]. ELECTRONICS & COMMUNICATIONS IN JAPAN, 1975, 58 (03): : 27 - 34
[2] An all-digital phase-locked loop demodulator based on FPGA
Gong, X. F.
Cui, Z. D.
[J]. 2017 3RD INTERNATIONAL CONFERENCE ON APPLIED MATERIALS AND MANUFACTURING TECHNOLOGY (ICAMMT 2017), 2017, 242
[3] BINARY QUANTIZED ALL-DIGITAL PHASE-LOCKED LOOP
YUKAWA, J
MORI, S
[J]. ELECTRONICS & COMMUNICATIONS IN JAPAN, 1973, 56 (12): : 21 - 28
[4] Phase-domain all-digital phase-locked loop
Staszewski, RB
Balsara, PT
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2005, 52 (03) : 159 - 163
[5] Direct Digital Synthesis-Based All-Digital Phase-Locked Loop
Vezant, Benoit
Mansuy, Cedric
Bui, Hung Tien
Boyer, Francois-Raymond
[J]. 2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 49 - +
[6] An FPGA-Based Linear All-Digital Phase-Locked Loop
Kumm, Martin
Klingbeil, Harald
Zipf, Peter
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (09) : 2487 - 2497
[7] All-Digital Phase-Locked Loop in Single Flux Quantum Circuit Technology
Cong, Haolin
Pedram, Massoud
[J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2022, 32 (03)
[8] A new all-digital phase-locked loop with high precision and low jitter
Chow, Hwang-Cherng
Su, Chung-Hsin
[J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2008, 95 (12) : 1241 - 1249
[9] SECOND-ORDER ALL-DIGITAL PHASE-LOCKED LOOP
HOLMES, JK
TEGNELIA, CR
[J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 1974, CO22 (01) : 62 - 68
[10] Design and Emulation of All-Digital Phase-Locked Loop on FPGA
Radhapuram, Saichandrateja
Yoshihara, Takuya
Matsuoka, Toshimasa
[J]. ELECTRONICS, 2019, 8 (11)

← 1 2 3 4 5 →