An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop

被引:3
|
作者
Namgoong, Won [1 ]
机构
[1] Univ Texas Dallas, Dept Elect Engn, Richardson, TX 75080 USA
基金
美国国家科学基金会;
关键词
Digital phase-locked loop; digitally controlled oscillator; Kalman filter; supply noise;
D O I
10.1109/TVLSI.2015.2426878
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With increased levels of integration in modern system-on-chips, the coupling of supply noise in a phase-locked loop (PLL) has become the dominant source of performance degradation in many systems. In this paper, an all-digital approach to canceling the effects of supply noise is presented. By sensing the supply noise using an analog-to-digital converter (ADC), an observer-controller loop filter jointly processes the ADC and phase detector outputs to determine the oscillator control signals that minimize the output jitter. The proposed digital PLL is shown to be significantly more robust to supply noise compared with a conventional PLL.
引用
收藏
页码:1025 / 1035
页数:11
相关论文
共 50 条
  • [1] A Digital Phase-Locked Loop With Background Supply Noise Cancellation
    Tseng, Yen-Min
    Yen, Yu-Chi
    Liu, Shen-Iuan
    2021 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2021,
  • [2] WIDEBAND ALL-DIGITAL PHASE-LOCKED LOOP
    YAMAMOTO, H
    MORI, S
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1975, 58 (03): : 27 - 34
  • [3] BINARY QUANTIZED ALL-DIGITAL PHASE-LOCKED LOOP
    YUKAWA, J
    MORI, S
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1973, 56 (12): : 21 - 28
  • [4] A 1.25GHz Fast-Locked All-Digital Phase-Locked Loop with Supply Noise Suppression
    Hung, Chao-Ching
    Chen, I-Fong
    Liu, Shen-Iuan
    2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 237 - 240
  • [5] Phase-domain all-digital phase-locked loop
    Staszewski, RB
    Balsara, PT
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2005, 52 (03) : 159 - 163
  • [6] An All-Digital Phase-Locked Loop for Digital Power Management Integrated Chips
    Chung, Yu-Ming
    Wei, Chia-Ling
    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2413 - 2416
  • [7] SECOND-ORDER ALL-DIGITAL PHASE-LOCKED LOOP
    HOLMES, JK
    TEGNELIA, CR
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1974, CO22 (01) : 62 - 68
  • [8] An all-digital phase-locked loop demodulator based on FPGA
    Gong, X. F.
    Cui, Z. D.
    2017 3RD INTERNATIONAL CONFERENCE ON APPLIED MATERIALS AND MANUFACTURING TECHNOLOGY (ICAMMT 2017), 2017, 242
  • [9] Design and Emulation of All-Digital Phase-Locked Loop on FPGA
    Radhapuram, Saichandrateja
    Yoshihara, Takuya
    Matsuoka, Toshimasa
    ELECTRONICS, 2019, 8 (11)
  • [10] The Implementation of An Adaptive Bandwidth All-Digital Phase-Locked Loop
    Chen, Chen-Feng
    Chau, Yawgeng A.
    TENCON 2010: 2010 IEEE REGION 10 CONFERENCE, 2010, : 1182 - 1185