10Gb/s clock extraction and data regeneration circuit implemented with phase-locked loop

被引：0
|
作者：
Yoo, TW
Park, MS
机构：
来源：
1997 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS I-III: HIGH FREQUENCIES IN HIGH PLACES | 1997年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A PLL clock-extraction and data-regeneration circuit(CEDAR) for 10 Gb/s optical transmission system was realized in a hybrid IC form. The jitter characteristics satisfied the recommendations of ITU-T. The CEDAR compensated against the temperature was tested for the temperature from -10 degrees C to 60 degrees C and showed no increase of error.
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页码：1713 / 1716
页数：4
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