Design and characterization of a 10 Gb/s clock and data recovery circuit implemented with phase-locked loop

被引：10

作者：

Song, JH ^{[1
]}

Yoo, TW ^{[1
]}

Ko, JH ^{[1
]}

Park, CS ^{[1
]}

Kim, JK ^{[1
]}

机构：

[1] ETRI, Opt Commun Dept, Taejon, South Korea

来源：

ETRI JOURNAL | 1999年 / 21卷 / 03期

关键词：

D O I：

10.4218/etrij.99.0199.0301

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A clock and data recovery circuit with a phase-locked Loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency- and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to 60 degrees C and showed no increase of error, This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

引用

页码：1 / 5

页数：5

共 50 条

[31] A CMOS 10Gb/s clock and data recovery circuit with a novel adjustable KPD phase detector
Chen, XY
Green, MM
[J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 301 - 304
[32] Optimal Design of Active Power Filter Phase-Locked Loop Circuit
Guo, Xifeng
Wang, Dazhi
Liu, Zhen
Wang, Xuming
[J]. 2012 ASIA-PACIFIC POWER AND ENERGY ENGINEERING CONFERENCE (APPEEC), 2012,
[33] A 4Gb/s CMOS fully-differiential analog dual delay locked loop clock/data recovery circuit
Mao, Z
Szymanski, TH
[J]. ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 559 - 562
[34] Ultrafast Phase Comparator for Phase-Locked Loop-Based Optoelectronic Clock Recovery Systems
Gomez-Agis, Fausto
Oxenlowe, Leif Katsuo
Kurimura, Sunao
Ware, Cedric
Mulvad, Hans Christian Hansen
Galili, Michael
Erasme, Didier
[J]. JOURNAL OF LIGHTWAVE TECHNOLOGY, 2009, 27 (13) : 2439 - 2448
[35] A Half-Rate 100 Gb/s Injection-Locked Clock/Data Recovery Circuit
Samavaty, Behzad
Green, Michael M.
[J]. 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2016,
[36] OPTIMIZATION OF PHASE-LOCKED LOOP PERFORMANCE IN DATA RECOVERY-SYSTEMS
CO, RS
MULLIGAN, JH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (09) : 1022 - 1034
[37] A 10-gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
Savoj, J
Razavi, B
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (05) : 761 - 768
[38] A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
Kwon, Dae-Hyun
Rhim, Jinsoo
Choi, Woo-Young
[J]. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16 (03) : 287 - 292
[39] 80 Gbit/s optical clock recovery with automatic lock acquisition using electrical phase-locked loop
Vehovc, S
Vidmar, M
Paoletti, A
[J]. ELECTRONICS LETTERS, 2003, 39 (08) : 673 - 674
[40] A 5.4 Gb/s Clock and Data Recovery Circuit Using the Seamless Loop Transition Scheme without Phase Noise Degradation
Lee, Won-Young
Kim, Lee-Sup
[J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 430 - 433

← 1 2 3 4 5 →