A Half-Rate 100 Gb/s Injection-Locked Clock/Data Recovery Circuit

被引：0
|
作者：
Samavaty, Behzad [1 ]
Green, Michael M. [1 ]
机构：
[1] Univ Calif Irvine, Dept EECS, Irvine, CA 92697 USA
来源：
2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2016年
关键词：
CMOS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 100 Gb/s clock/data recovery circuit using a highspeed BiCMOS process is designed and simulated. In this circuit a half-rate 50 GHz clock signal, injected in parallel with the tail current of an LC VCO, locks to a 100 Gb/s input NRZ data signal. Inductive tuning for the frequency tuning of the VCO is employed, which gives a wide frequency tuning range while maintaining a constant quality factor.
引用
收藏
页数：4
相关论文
共 50 条
  • [1] An 8-Gb/s half-rate clock and data recovery circuit
    Khalek, Faizal
    Sulaiman, Mohd-Shahiman
    Yusoff, Zubaida
    [J]. EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 535 - 538
  • [2] A 1.25Gb/s half-rate clock and data recovery circuit
    Yan, CY
    Lee, CH
    Lee, Y
    [J]. 2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION & TEST (VLSI-TSA-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 116 - 119
  • [3] Injection-locked clock recovery using a multiplexed oscillator for half-rate data-recovered applications
    Yang, Ching-Yuan
    Chang, Ken-Hao
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2008, E91A (01): : 409 - 412
  • [4] A 7 GB/S HALF-RATE CLOCK AND DATA RECOVERY CIRCUIT WITH COMPACT CONTROL LOOP
    Cheng, Yu-Po
    Lee, Yen-Long
    Chien, Ming-Hung
    Chang, Soon-Jyh
    [J]. 2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2016,
  • [5] A 2.5-Gb/s half-rate clock and data recovery circuit with a digital quadricorrelator frequency detector
    Tang Shimin
    Chen Jihua
    Chen Nuxing
    Feng Yingjie
    [J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 604 - 607
  • [6] A 4-Gb/s half-rate clock and data recovery circuit with a 3-stage VCO
    Zhuang, JC
    Du, QJ
    Kwasniewski, T
    [J]. PROCEEDINGS OF THE THIRD IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS, 2005, : 128 - 131
  • [7] A 10-gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
    Savoj, J
    Razavi, B
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (05) : 761 - 768
  • [8] A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector
    Savoj, J
    Razavi, B
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (01) : 13 - 21
  • [9] A 10Gb/s CMOS half-rate clock and data recovery circuit with direct bang-bang tuning
    Chen, Tun-Shih
    [J]. 2005 IEEE International Workshop on Radio-Frequency Integration Technology, Proceedings: INTEGRATED CIRCUITS FOR WIDEBAND COMMUNICATION AND WIRELESS SENSOR NETWORKS, 2005, : 57 - 60
  • [10] A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation
    Yang, Ching-Yuan
    Lin, Jung-Mao
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2007, E90C (01): : 196 - 200
12345