A 4-Gb/s half-rate clock and data recovery circuit with a 3-stage VCO

被引：0

作者：

Zhuang, JC ^{[1
]}

Du, QJ ^{[1
]}

Kwasniewski, T ^{[1
]}

机构：

[1] Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada

来源：

PROCEEDINGS OF THE THIRD IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS | 2005年

关键词：

clock data recovery; phase detector; frequency detector; frequency acquisition;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 4-Gb/s half-rate clock and data recovery circuit (CDR) with a 3-stage voltage-controlled oscillator (VCO), and a novel phase/frequency detector (PFD) is reported in this paper. The VCO produces multiple-phase clocks spaced by one-third of the incoming data symbol period. A novel PFD is employed to compare the multiple-phase clocks with the incoming data and produce the error signals to tune the VCO frequency with the aid of a charge pump and a loop filter. The PFD also produces a signal to enlarge the charge pump current during the frequency acquisition stage so that a fast frequency acquisition can be achieved. This CDR was implemented in CMOS 0.18 mu m technology and its feasibility was confirmed by post-layout simulations.

引用

页码：128 / 131

页数：4

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