A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

被引：113

作者：

Savoj, J ^{[1
]}

Razavi, B ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 01期

关键词：

bang-bang phase detector; clock and data recovery; frequency detector; ring oscillator; voltage-controlled oscillator (VCO);

D O I：

10.1109/JSSC.2002.806284

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-mum CMOS technology in an area of 1.75 x 1.55 mm(2), the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10(-9) with a pseudorandom bit sequence of 2(23) - 1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.

引用

页码：13 / 21

页数：9

共 50 条

[1] A 10-gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
Savoj, J
Razavi, B
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (05) : 761 - 768
[2] A 10-gb/s CMOS clock and data recovery circuit
Savoj, J
Razavi, B
[J]. 2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2000, : 136 - 139
[3] A 2.5-Gb/s half-rate clock and data recovery circuit with a digital quadricorrelator frequency detector
Tang Shimin
Chen Jihua
Chen Nuxing
Feng Yingjie
[J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 604 - 607
[4] A CMOS clock and data recovery circuit with a half-rate three-state phase detector
Yang, Ching-Yuan
Lee, Yu
Lee, Cheng-Hsing
[J]. IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (06): : 746 - 752
[5] Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit
Shin, JK
Yoo, TW
Lee, MS
[J]. 7th International Conference on Advanced Communication Technology, Vols 1 and 2, Proceedings, 2005, : 205 - 210
[6] A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
Kreienkamp, R
Langmann, U
Zimmermann, C
Aoyama, T
[J]. PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 73 - 76
[7] A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
Kreienkamp, R
Langmann, U
Zimmermann, C
Aoyama, T
Siedhoff, H
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (03) : 736 - 743
[8] An 8-Gb/s half-rate clock and data recovery circuit
Khalek, Faizal
Sulaiman, Mohd-Shahiman
Yusoff, Zubaida
[J]. EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 535 - 538
[9] A 1.25Gb/s half-rate clock and data recovery circuit
Yan, CY
Lee, CH
Lee, Y
[J]. 2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION & TEST (VLSI-TSA-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 116 - 119
[10] A 10Gb/s CMOS half-rate clock and data recovery circuit with direct bang-bang tuning
Chen, Tun-Shih
[J]. 2005 IEEE International Workshop on Radio-Frequency Integration Technology, Proceedings: INTEGRATED CIRCUITS FOR WIDEBAND COMMUNICATION AND WIRELESS SENSOR NETWORKS, 2005, : 57 - 60

← 1 2 3 4 5 →