Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit

被引：2
|
作者：
Shin, JK [1 ]
Yoo, TW [1 ]
Lee, MS [1 ]
机构：
[1] Informat & Commun Univ, Sch Engn, Taejon 305714, South Korea
来源：
7th International Conference on Advanced Communication Technology, Vols 1 and 2, Proceedings | 2005年
关键词：
optical receiver; clock and data recovery; half-rate phase detector; MOS current mode logic; CMOS integrated circuit design;
D O I：
10.1109/ICACT.2005.245826
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A 10Gb/s Clock and data recovery (CDR) circuits which extract the clock signal from non-return-zero (NRZ) random data stream are very important to the 10-gigabit -per-second integrated receivers. The half-rate linear phase detector for 10-Gb/s clock and data recovery (CDR) circuit is designed to 0.18-um standard CMOS technology. This half-rate phase detector is composed of four latches and two exclusive OR (XOR) gates. The proposed circuits of phase detector provide a linear characteristic and it has a configuration of MOS current-mode logic (MCML) gates.
引用
收藏
页码：205 / 210
页数：6
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