A 10-gb/s CMOS clock and data recovery circuit

被引：6
|
作者：
Savoj, J [1 ]
Razavi, B [1 ]
机构：
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90024 USA
来源：
2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年
关键词：
D O I：
10.1109/VLSIC.2000.852871
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 10-Gb/s phase-locked clock and data recovery circuit incorporates a 5-GHz interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-mu m CMOS technology, the circuit exhibits an rms jitter of 6.6 ps in the recovered clock with random data input of length 2(23)-1. The power dissipation is 99 mW from a 2.6-V supply.
引用
收藏
页码：136 / 139
页数：4
相关论文
共 50 条
  • [1] A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
    Kreienkamp, R
    Langmann, U
    Zimmermann, C
    Aoyama, T
    [J]. PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 73 - 76
  • [2] A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
    Kreienkamp, R
    Langmann, U
    Zimmermann, C
    Aoyama, T
    Siedhoff, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (03) : 736 - 743
  • [3] Clock and data recovery circuit for 10-Gb/s asynchronous optical packets
    Kanellos, GT
    Stampoulidis, L
    Pleros, N
    Houbavlis, T
    Tsiokos, D
    Kehayas, E
    Avramopoulos, H
    Guekos, G
    [J]. IEEE PHOTONICS TECHNOLOGY LETTERS, 2003, 15 (11) : 1666 - 1668
  • [4] A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
    Rhee, W
    Ainspan, H
    Rylov, S
    Rylyakov, A
    Beakes, M
    Friedman, D
    Gowda, S
    Soyuer, M
    [J]. PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 81 - 84
  • [5] A 10-gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
    Savoj, J
    Razavi, B
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (05) : 761 - 768
  • [6] A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector
    Savoj, J
    Razavi, B
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (01) : 13 - 21
  • [7] A 10-Gb/s Power and Area Efficient Clock and Data Recovery Circuit in 65-nm CMOS Technology
    Rhim, Jinsoo
    Choi, Kwang-Chun
    Choi, Woo-Young
    [J]. 2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2012, : 104 - 107
  • [8] Equalization and clock and data recovery techniques for 10-gb/s CMOS serial-link receivers
    Gondi, Srikanth
    Razavi, Behzad
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (09) : 1999 - 2011
  • [9] A Monolithic 10 Gb/s Clock and Data Recovery Circuit
    Hou Fenfei
    Cao Xiaowei
    [J]. 2008 CHINA-JAPAN JOINT MICROWAVE CONFERENCE (CJMW 2008), VOLS 1 AND 2, 2008, : 436 - +
  • [10] A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
    Kwon, Dae-Hyun
    Rhim, Jinsoo
    Choi, Woo-Young
    [J]. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16 (03) : 287 - 292
12345