A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

被引：113
|
作者：
Savoj, J [1 ]
Razavi, B [1 ]
机构：
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 01期
关键词：
bang-bang phase detector; clock and data recovery; frequency detector; ring oscillator; voltage-controlled oscillator (VCO);
D O I：
10.1109/JSSC.2002.806284
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-mum CMOS technology in an area of 1.75 x 1.55 mm(2), the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10(-9) with a pseudorandom bit sequence of 2(23) - 1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.
引用
收藏
页码：13 / 21
页数：9
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