A Half-rate Bang-bang Clock and Data Recovery Circuit for 56 Gb/s PAM4 Receiver in 65 nm CMOS

A half-rate clock and data recovery (CDR) circuit used in a 56 Gb/s PAM4 receiver is presented. The CDR consists of a half-rate Alexander phase detector (PD), a V/I convertor, a loop filter and an LC quadrature voltage-controlled oscillator (LC-QVCO). Because PD dominates the power consumption of CDR, a half-rate architecture is employed to reduce the operation speed of D flip-flop(DFF). The cost is only a little overhead in power and complexity in a quadrature clock design. In addition, to achieve higher gain and good performance, synchronization DFFs are added in PD design. The CDR is implemented in 65 nm CMOS process, and the total area including the pads is about 0.56 mm2. Post-simulation shows that the peak-to-peak jitter of CDR is only 1.23 ps (0.017 UI). The whole system draws a current of 37.56 mA under a 1.2 V supply, that is, consumes 45 mW.