A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

被引：0

作者：

Zhao, Xiaoteng ^{[1
]}

Chen, Yong ^{[1
]}

Mak, Pui-In ^{[1
]}

Martins, Rui P. ^{[1
]}

机构：

[1] Univ Macau, State Key Lab Analog & Mixed Signal VLSI & IME FS, Macau, Peoples R China

来源：

2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019) | 2019年

关键词：

4-/8-level pulse amplitude modulation (PAM-4/8); bang-bang phase detector (BBPD); clock and data recovery (CDR); non-return to zero (NRZ); StrongARM comparator; XOR; voltage-to-current (V/I) converter; half rate;

D O I：

10.1109/apccas47518.2019.8953158

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports a trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit featuring single-loop phase tracking, and low-power techniques at both the architecture and circuit levels to improve the overall energy efficiency. Fabricated in 28-nm CMOS, the prototype achieves a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s in NRZ/PAM-4/PAM-8 modes, respectively. The integrated jitter is <0.53 ps, and at least 1-UIpp jitter tolerance is achieved up to 10 MHz for all the three modes.

引用

页码：229 / 232

页数：4

共 12 条

[1] A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS
Zhao, Xiaoteng
Chen, Yong
Mak, Pui-In
Martins, Rui P.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (01) : 89 - 102
[2] A Half-rate Bang-bang Clock and Data Recovery Circuit for 56 Gb/s PAM4 Receiver in 65 nm CMOS
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[3] A 10Gb/s CMOS half-rate clock and data recovery circuit with direct bang-bang tuning
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[4] A 10 Gb/s PAM4 receiver with reference-less half-rate Bang-Bang CDR in 180-nm CMOS
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[7] A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS
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[8] A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
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Kneuper, Pascal
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[9] A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS
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[10] A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS
Zhao, Xiaoteng
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