A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

被引：0
|
作者：
Zhao, Xiaoteng [1 ]
Chen, Yong [1 ]
Mak, Pui-In [1 ]
Martins, Rui P. [1 ]
机构：
[1] Univ Macau, State Key Lab Analog & Mixed Signal VLSI & IME FS, Macau, Peoples R China
来源：
2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019) | 2019年
关键词：
4-/8-level pulse amplitude modulation (PAM-4/8); bang-bang phase detector (BBPD); clock and data recovery (CDR); non-return to zero (NRZ); StrongARM comparator; XOR; voltage-to-current (V/I) converter; half rate;
D O I：
10.1109/apccas47518.2019.8953158
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper reports a trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit featuring single-loop phase tracking, and low-power techniques at both the architecture and circuit levels to improve the overall energy efficiency. Fabricated in 28-nm CMOS, the prototype achieves a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s in NRZ/PAM-4/PAM-8 modes, respectively. The integrated jitter is <0.53 ps, and at least 1-UIpp jitter tolerance is achieved up to 10 MHz for all the three modes.
引用
收藏
页码：229 / 232
页数：4
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