A 10Gb/s CDR with a half-rate bang-bang phase detector

被引：0

作者：

Ramezani, M ^{[1
]}

Salama, CAT ^{[1
]}

机构：

[1] Univ Toronto, Edward S Rogers Sr Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 10Gb/s PLL-based Clock and Data Recovery (CDR) circuit, with a half-rate bang-bang phase detector. is implemented using a 0.13mum CMOS technology. The clock frequency is 5GHz, generated using a fully differential four-stage VCO. The loop filter is implemented on chip. The design meets the requirements of the local area network (LAN) applications. The total power dissipation of the CDR is less than 150mW.

引用

页码：181 / 184

页数：4

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