A Half-Rate 100 Gb/s Injection-Locked Clock/Data Recovery Circuit

被引：0

作者：

Samavaty, Behzad ^{[1
]}

Green, Michael M. ^{[1
]}

机构：

[1] Univ Calif Irvine, Dept EECS, Irvine, CA 92697 USA

来源：

2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2016年

关键词：

CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 100 Gb/s clock/data recovery circuit using a highspeed BiCMOS process is designed and simulated. In this circuit a half-rate 50 GHz clock signal, injected in parallel with the tail current of an LC VCO, locks to a 100 Gb/s input NRZ data signal. Inductive tuning for the frequency tuning of the VCO is employed, which gives a wide frequency tuning range while maintaining a constant quality factor.

引用

页数：4

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